The present invention relates to a fabrication method of semiconductor devices, and particularly to a growth method of epitaxial layers for fabricating MOS (metal Oxide Semiconductor) transistors.
Seeking finer integration and higher performance of CMOS (Complementary MOS) LSI (Large Scale Integrated circuits), miniaturization of MOSFETs (MOS Field Effect Transistors) has been pursued, and MOSFETs having gate electrode of 0.25 .mu.m are developed now. Along with the miniaturization of MOSFETs, innovation of gate electrode structure of the CMOS LSI is also required.
Conventionally, n-type semiconductor is used for gate electrodes of MOSFETs in the CMOS LSI regardless of difference of conductivity type, namely difference between nMOSFET (n-type MOSFET) and pMOSFET (p-type MOSFET), because of convenience in their fabrication processes. For example, just after configuring a gate insulation film, a poly-crystal silicon layer is deposited and phosphorus diffusion is performed to obtain the n-type semiconductor for the gate electrodes. According to these fabrication processes, a buried-channel type pMOSFET having gate electrode of n-type semiconductor is obtained.
However, the short-channel-effect becomes dominant in the buried-type pMOSFET, which causes a problem that the threshold voltage is highly affected from gate length dispersion accompanying the fabrication processes. This threshold voltage dispersion makes circuit operation unstable and restricts circuit design of the CMOS LSI, without saying of yield-rate degradation.
For evading this problem, threshold voltage is heretofore designed to be certainly high in the pMOSFET according to the conventional fabrication processes. However, in the CMOS LSI being developed now, which has MOSFETs of gate electrodes shorter than 0.25 .mu.m, power supply voltage is to be set under 2.5V instead of former standard of 5V or 3.3V, the threshold voltage being forced to be designed lower than before.
This miniaturization of MOSFETs, and consequently, reduction of gate length and operation voltage should continue, needing further reduction of the threshold voltage. This is the reason that a practical fabrication method of the surface-channel type pMOSFET having a gate electrode of p-type semiconductor is waited now. In other words, the p-n gate CMOS LSI having nMOSFETs with n-type gate electrode and pMOSFETs with p-type gate electrode will be the main current hereafter.
However, for developing the above p-n gate CMOS LSI, it is inevitable to resolve following problems accompanying the impurity injection into the gate electrode.
In the p-n gate CMOS LSI, complementary gate electrodes have inverse conductivity with each other and cannot be injected with impurities by way of conventional methods such as phosphorus diffusion. Therefore, the gate electrodes are made active electrically by injecting impurity ions therein by way of an ion injection process performed when configuring source and drain electrodes of the MOSFETs. However, the injected impurity ions may often reach, by channelling, up to the gate insulation film or sometimes up to the channel region of the MOSFETs.
Results of an examination performed by us show that this channelling phenomenon is found predominantly in gate electrodes which are configured by patterning deposited and crystallized amorphous silicon, and it is confirmed that the channeling gives an abnormal kink on the sub-threshold characteristic curve of nMOSFET having gate length shorter than 0.5 .mu.m.
It is also found that the abnormal kink is owing to column-like crystal grains formed in the amorphous silicon layer grown until the layer depth when the amorphous silicon layer is thermo-processed after deposition. Passing through boundaries of the crystal grains having orientation easy to be channelled, arsenic attains into a part of the channel region of the nMOSFETs when arsenic-ion injection process is performed afterwards for making active the gate electrodes.
The appearance of the abnormal kink in the sub-threshold characteristic is also deeply depending on the grain size, and it is when the grains, provoking the channelling of injected ions, show a bamboo-structure against the gate electrode that the abnormal kink is observed.
Prevention of the channeling is important because this phenomenon makes control of the MOSFET threshold voltage very difficult and degrades reliability of the gate insulation film as well.
Although it is not intending to configure the p-n gate structure, there is a prior art for preventing impurities to diffuse by channelling until the channel region in the ion injection process, by making amorphous the surface region of the injection object, which is disclosed in a Japanese patent application laid open as Provisional Publication No. 191070/'86.
FIGS. 18A to 18E are cross sections schematically illustrating fabrication processes of a semiconductor device disclosed in the above patent application.
Referring to FIGS. 18A to 18E, on a p-type substrate 21 having a separation region 22, a poly-crystal silicon layer 24 is deposited after forming an insulation film 23. After phosphorus diffusion, surface region 25 of the poly-crystal silicon layer 24 is made amorphous by silicon ion injection. After patterning of the gate electrode 26, n.sup.+ and n.sup.- regions are formed by ion injection. Then, a sidewall 30 is configured by depositing a silicon-oxide layer and etching it back by way of anisotropic etching, which is followed by ion injection for introducing impurities into the gate electrode and configuring the source and the drain electrode.
Thus, the channelling of injected ions is suppressed in the prior art, by providing an amorphous region 25 on the surface of the gate electrode protected with a sidewall.
However, insulation materials to be used for configuring the sidewall 30 are limited within those which can be deposited at a temperature that may not cause re-crystallization of the amorphous silicon layer, in the prior art according to above processes. Practically saying, the applicable insulation material for configuring the sidewall is limited into either a low grade silicon-oxide film obtained from O.sub.3 /TEOS (tetra-ethoxy-silane) or a silicon-oxide film of insufficient step-coverage performance obtained from O.sub.2 /SiH.sub.4.
When the silicon-oxide film is deposited with O.sub.3 /TEOS, it provokes degradation of hot-carrier life because of H.sub.2 O included therein. When it is deposited with O.sub.2 /SiH.sub.4, on the other hand, effective channel lengths of MOSFETs become unequal owing to dispersion of sidewall thickness depending on element layouts such as spaces between gate electrodes of the CMOS LSI, because of the bad step-coverage performance, resulting in instability of the device characteristic.